Tensilica Inc. has introduced two configurable processor cores, the Xtensa LX2 and Xtensa 7, both of which include on-the-fly error correcting code. Both are also said to reduce power up to 30% in total core plus memory power, and to include power-down modes.

The seventh-generation Xtensa 7 is optimized for low-power control and digital signal processor applications. It offers a 32-bit architecture with a 5-stage pipeline, a 32-bit arithmetic logic unit (ALU), up to 64 general-purpose physical registers, six special purpose registers and 80 base instructions. Its clock speed reaches 600 MHz. The second-generation Xtensa LX2 includes all of the features of Xtensa 7 plus significantly faster data input and output (I/O), the ability to issue multiple instructions per-cycle in a manner similar to very long instruction word (VLIW) processors, and an optional 7-stage pipeline.